1. Field of the Invention
The present invention relates to the design of erasable and programmable non-volatile memory integrated circuits; and more particularly to circuits for programing and pre-programming memory cells in the device, suited for FLASH EPROM or EEPROM memory cells.
2. Description of Related Art
Non-volatile memory design based on integrated circuit technology represents an expanding field. One popular class of non-volatile memory cell is known as electrically erasable-programmable read only memory (EEPROM), which includes standard EEPROM and FLASH EPROM designs.
Both the FLASH EPROM and EEPROM technologies are based on a memory transistor which consists of a source, channel, and drain with a floating gate over the channel and a control gate isolated from the floating gate. The act of programming the cell involves charging the floating gate with electrons, which causes the turn on threshold of the memory cell to increase. FLASH EPROM typically uses a hot electron programing technique to charge the cells. When programmed the cell will not turn on, that is it will remain non-conductive, when addressed with a read potential applied to its control gate. The act of erasing the cell involves removing electrons from the floating gate to lower the threshold. With the lower threshold, the cell will turn on to a conductive state when addressed with a read potential to the control gate.
The programming and erasing modes for FLASH EPROMS according to the prior art are described in U.S. Pat. No. 5,053,990, invented by Kreifels, et al. See also, U.S. Pat. No. 4,875,118, entitled VOLTAGE MARGINING CIRCUIT FOR FLASH EPROM, invented by Jungroth; and Am28F020, 262,144.times.8 Bit CMOS Flash Memory, Advance Information, Advanced Micro Devices, Inc., March 1991.
In addition, the prior art techniques for erasing floating gate memory cells involve erasing the entire memory array in one operation.
In order to erase a cell, and insure that the right amount of charge is removed from the entire block being erased, all cells in the chip are pre-programmed to a known state (00 hex). This way, when the chip is erased, all of the memory cells will start with substantially the same amount of charge in the floating gate. However, the pre-programming stage in a chip erase operation takes a substantial amount of time. Each byte in the block to be erased must be programmed, and then the success of programming verified. Only after the entire chip has been pre-programmed and verified, can the erase operation occur.
Thus, it is desirable to provide a fast programming and pre-programming technique for floating gate memory devices, such as FLASH EPROMs.